// Copyright (C) 1953-2022 NUDT
// Verilog module name - stream_remapping 
// Version: V4.1.0.0.20230103
// Created:
//         by - fenglin 
////////////////////////////////////////////////////////////////////////////
// Description:
//         discard c-tag and r-tag.
///////////////////////////////////////////////////////////////////////////

`timescale 1ns/1ps

module stream_remapping
(
        i_clk  ,
        i_rst_n,                
        
        iv_data,
        i_data_wr,
        o_data_ready,
        
        ov_data,
        o_data_wr,
        i_data_ready        
);

// I/O
// clk & rst
input                  i_clk;   
input                  i_rst_n;
//tsntag & bufid input from host_port
(*MARK_DEBUG="true"*)input       [8:0]      iv_data             ;
(*MARK_DEBUG="true"*)input                  i_data_wr           ;
                     output                 o_data_ready        ;
// transmit pkt to phy     
(*MARK_DEBUG="true"*)output      [8:0]      ov_data     ;
(*MARK_DEBUG="true"*)output                 o_data_wr   ;
                     input                  i_data_ready;

wire          [8:0]      wv_data_ptd2fifo             ;
wire                     w_data_wr_ptd2fifo           ;
wire          [3:0]      wv_fifo_usedw_fifo2ptd       ;

wire                     w_fifo_rd_poc2fifo    ;
wire          [8:0]      iv_fifo_rdata_fifo2poc; 
packet_tag_discard packet_tag_discard_inst
(
.i_clk           (i_clk  ),
.i_rst_n         (i_rst_n),                
 
.iv_data         (iv_data         ),
.i_data_wr       (i_data_wr       ),
.o_data_ready    (o_data_ready    ),
 
.ov_data         (wv_data_ptd2fifo      ),
.o_data_wr       (w_data_wr_ptd2fifo    ),
.iv_fifo_usedw   (wv_fifo_usedw_fifo2ptd)     
);
//altera ip

syncfifo_showahead_aclr_w9d16 syncfifo_showahead_aclr_w9d16_inst(
.data      (wv_data_ptd2fifo), 
.wrreq     (w_data_wr_ptd2fifo),
.rdreq     (w_fifo_rd_poc2fifo),
.clock     (i_clk),
.aclr      (!i_rst_n),
.q         (iv_fifo_rdata_fifo2poc),   
.usedw     (wv_fifo_usedw_fifo2ptd),
.full      (),
.empty     () 
); 

//xilinx ip 
/*
syncfifo_showahead_aclr_w9d16 syncfifo_showahead_aclr_w9d16_inst(
    .din   (wv_data_ptd2fifo      ), 
    .wr_en (w_data_wr_ptd2fifo    ),
    .rd_en (w_fifo_rd_poc2fifo),
    .clk   (i_clk),
    .srst  (!i_rst_n), 
    .dout  (iv_fifo_rdata_fifo2poc),    
    .data_count (wv_fifo_usedw_fifo2ptd),
    .full  (), 
    .empty () 
);
*/

packet_output_control packet_output_control_inst
(
.i_clk         (i_clk        ),
.i_rst_n       (i_rst_n      ),                
                
.iv_fifo_usedw (wv_fifo_usedw_fifo2ptd),
.o_fifo_rd     (w_fifo_rd_poc2fifo    ),
.iv_fifo_rdata (iv_fifo_rdata_fifo2poc),
                
.ov_data       (ov_data      ),
.o_data_wr     (o_data_wr    ),
.i_data_ready  (i_data_ready )      
);
endmodule